In a wafer-level packaging process of semiconductor, a wafer is cut into a plurality of chips, from which good chips are selected and are reallocated on a surface of substrate for subsequent processes. In the process of reallocation, for sake of precision manufacturing, the precision of chip placement and chip arrangement are with extremely strict requirements, i.e., usually with accuracy about some microns or even less. In order to ensure the high accuracy of chip placing, in the conventional chip-placing method, an image capturing device is configured to record a position error of chips on each to-be-placed locations of the substrate. An average error is obtained from the position errors of all to-be-placed locations derived after repeating several times. The average error is applied to compensate the relative position of the chip in relation to the substrate when the chip is placed.
However, the above conventional method is required to be repeated a plurality of times in order to establish the error average of the to-be-placed locations on the substrate. Moreover, when a new error factor is generated, such as thermal deformation caused by temperature changes, the error cannot be corrected in time to cause that the error average of the to-be-placed locations on the substrate must be re-established. Therefore, the conventional chip-placing method cannot be performed efficiently and cannot fit to instantly achieve a more strict requirement in terms of accuracy and precision. Furthermore, in EPO patent publication number 1802192, it discloses a method for mounting a flip chip on a substrate. However, a chip gripper and a reference mark used in the method are not separately disposed in a distance with each other. The method of the EPO application causes a problem that, in order to perform an alignment, it requires to provide additional alignment patterns around the chip which is gripped by the chip gripper.